1. Field of the Invention
The present invention relates to a driving circuit of a semiconductor display device. More particularly, the present invention relates to a circuit for generating an analog signal or a digital signal to be inputted to a source signal line driving circuit of a semiconductor display device. More particularly, the present invention relates to a circuit for processing a parallel analog or a digital divided signal outputted from a dividing circuit for performing serial-to-parallel conversion (Serial-to-Parallel Conversion Circuit: SPC) before it is inputted to a source signal line driving circuit. The present invention also relates to a semiconductor display device having a circuit for generating an analog signal or a digital signal to be inputted to a source signal line driving circuit.
2. Description of the Related Art
Technology for manufacturing a semiconductor device formed on an insulating substrate using a semiconductor thin film, for example, a thin film transistor (TFT), has rapidly developed these days. The reason for it is the growing demand for a semiconductor display device using semiconductor devices (representatively, an active matrix semiconductor display device). It is to be noted that an insulating substrate having a semiconductor device formed on the surface thereof is herein referred to as an active matrix substrate.
An active matrix semiconductor display device displays an image by controlling, with TFTs of the pixels, charge of several hundreds of thousands of or several million pixel electrodes arranged to be matrix-like.
A driving circuit of an active matrix semiconductor display device is required to operate at high speed. Among driving circuits, in particular, a source signal line driving circuit is required to input signals sequentially to all the pixel TFTs connected to a gate signal line during a time period when a signal is inputted to the gate signal line. The source signal line driving circuit is thus required to operate at higher speed than the speed at which the gate signal line driving circuit operates. For example, in case of a VGA active matrix semiconductor display device, the driving frequency of the source signal line driving circuit is typically about 20 MHz.
An active matrix semiconductor display device is expected to display images having many tones with a high precision and with a high resolution, which invokes the tendency for the number of pixels in the horizontal direction (horizontal number of pixels: Hn) of the active matrix semiconductor display device to increase.
As the horizontal number of pixels Hn increases, the source signal line driving circuit is required to be operated at higher speed. If the operating speed of the source signal line driving circuit is lowered, the image display speed is lowered, and thus, various problems such as flicker of the displayed image are caused.
In order to increase the horizontal number of pixels of the active matrix semiconductor display device while the above-mentioned various problems are avoided, it is necessary to make higher the driving frequency of the source signal line driving circuit. However, as the driving frequency of the source signal line driving circuit is made higher, the response time of TFTs of the source signal line driving circuit may not keep up with the driving frequency of the source signal line driving circuit, which may make the operation impossible or may lower the reliability.
Accordingly, in order to suppress the driving frequency of the source signal line driving circuit without lowering the image display speed, a dividedly driving method is conventionally used. Divided driving is a driving method where pixels arranged in the horizontal direction are divided into m groups, and a signal having image information is simultaneously inputted to the respective groups of the pixels during one line period.
It is to be noted that, as used herein, the term xe2x80x9cone line periodxe2x80x9d means a time period from a time point when a signal having image information is inputted to a first pixel of pixels in one line arranged in the horizontal direction to a time point just before a signal having image information is inputted to a first pixel of the next line.
In case of driving divided into m (m is a positive number larger than 1, generally a natural number), if the length of one line period is the same as in the case where no dividing is performed, the period where a signal having image information (an image signal) is inputted per pixel is m times as long as that in the case where no dividing is performed. This means that the driving frequency of the source signal line driving circuit becomes 1/m, and thus, it is possible to lower the driving frequency of the source signal line driving circuit such that the source signal line driving circuit is completely operable.
In case of driving divided into m, video signals (divided video signals) having image information corresponding to m pixels, respectively are sampled by the source signal line driving circuit, and are simultaneously inputted as m image signals to the respective m pixels.
Divided video signals to be inputted to the source signal line driving circuit are, generally, generated by a circuit group provided on an IC chip (a semiconductor circuit formed of MOSFETs formed on single crystalline silicon) connected through an FPC (a flexible print circuit) to an active matrix substrate. FIG. 17 illustrates a circuit group for generating divided video signals to be inputted to a source signal line driving circuit in an analog-driven active matrix semiconductor display device.
Reference numerals 901, 902, 903, 904, 905, and 906 denote a control circuit, an A/D conversion circuit, a xcex3 correction circuit, a D/A conversion circuit, a dividing circuit, and a buffer circuit group, respectively.
An Hsync signal and a Vsync signal are inputted to the control circuit 901. A clock signal (CK), a start pulse signal (SP), and the like for driving the source signal line driving circuit are inputted from the control circuit 901 to the source signal line driving circuit. Further, signals for driving the A/D conversion circuit 902, the xcex3 correction circuit 903, the D/A conversion circuit 904, and the dividing circuit 905 are inputted from the control circuit 901 to the respective circuits.
An analog video signal having image information is inputted to the A/D conversion circuit 902. The analog video signal inputted to the A/D conversion circuit 902 is converted to a digital video signal and is inputted to the xcex3 correction circuit 903. The digital video signal inputted to the xcex3 correction circuit 903 is inputted to the D/A conversion circuit 904 after xcex3 correction. The digital video signal inputted to the D/A conversion circuit 904 is again converted to an analog video signal and is inputted to the dividing circuit 905.
The analog video signal inputted to the dividing circuit 905 is subject to serial-parallel conversion, and is converted to divided video signals into the number of which is the same as the number of divisions of the divided driving. In case of driving divided into m, the analog video signal is converted to m divided video signals.
The m divided video signals are inputted to the buffer circuit group 906. The buffer circuit group 906 has buffer circuits 906_1-906_m, and the m divided video signals are inputted to the corresponding buffer circuits 906_1 to 906_m, respectively.
By the way, when a signal outputted from a certain circuit is inputted to another circuit, the leading edge or the trailing edge of the signal is sometimes obtuse such that the waveform of the signal can not be rectangular or the potential and the amplitude of the signal may be changed. This is because of the existence of load capacity (parasitic capacitance) in the circuit where the signal is inputted. This is a phenomenon which is observed more outstandingly as the number of circuit elements of the circuit where the signal is inputted increases and the structure of the circuit becomes more complicated accordingly. A buffer circuit is a circuit which, when a signal outputted from a certain circuit is inputted to another circuit, performs buffering and amplification without change in the waveform, potential, and amplitude in the signal.
The m divided video signals are buffered and amplified by the buffer circuits 906_1 to 906_m, and are inputted to the source signal line driving circuit. Then, in case of an analog-driven active matrix semiconductor display device, the m divided video signals are sampled by the source signal line driving circuit, and are inputted as m image signals to the corresponding pixels through the source signal lines.
All of the buffer circuits 906_1 to 906_m of the buffer circuit group 906 are theoretically of the same structure. However, actually, the characteristics of the individual buffer circuits are not completely the same. Depending on the buffer circuit, the extent of the amplification of the amplitude (amplification ratio) of the outputted signal may be different from that of the inputted signal, or the outputted signal may have an offset potential. The characteristics of a buffer circuit depend on the manufacturing error of circuit elements of the buffer circuit and the ambient temperature of the buffer circuit.
Therefore, the potential and the amplitude of a divided video signal outputted from a buffer circuit is always influenced by the characteristics of the buffer circuit. It follows that a divided video signal outputted from a buffer circuit having different characteristics has amplitude different from those of other divided video signals or has an offset potential, and has potential difference from other divided video signals.
When a divided video signal having potential difference is sampled by the source signal line driving circuit, the image signal inputted to a pixel by the sampling also has potential difference. The potential difference of the image signal is displayed as a brighter or darker portion, and a stripe due to the brightness/darkness (a division stripe) is visually recognized by an observer.
In view of the above, an object of the present invention is to provide an active matrix semiconductor display device capable of displaying an image having many tones with a high precision and with a high resolution where a division stripe is unliable to be visually recognized by an observer during dividedly driving.
The inventor of the present invention thought that a division stripe was visually recognized by an observer because a brighter portion or a darker portion displayed on a screen due to the potential difference in the image signal always appeared in pixels connected to a particular source signal line. The inventor of the present invention further thought that this was because a plurality of divided video signals outputted from a dividing circuit are always inputted to particular buffer circuits corresponding to the respective divided video signals.
According to the present invention, a plurality of divided video signals outputted from a dividing circuit are not always inputted to particular buffer circuits, respectively, but are inputted to different buffer circuits in every different time period. More specifically, a plurality of divided video signals to be inputted biuniquely correspond to a plurality of buffer circuits to which the divided video signals are inputted, respectively, and the plurality of buffer circuits corresponding to the plurality of divided video signals, respectively, replace one another every time when a predetermined time period elapses. In other words, the combination of the divided video signals and the buffer circuits is changed every time when a predetermined time period elapses.
Because of the above-described structure, even if a division stripe is displayed on the screen due to potential difference between a divided video signal outputted from a buffer circuit having different characteristics and other divided video signals, since the place where the division stripe is displayed moves every time when a predetermined time period elapses, the division stripe is unliable to be visually recognized by an observer.
It is to be noted that, in the present invention, to set the number of patterns of the combination of the divided video signals and the buffer circuits, and the time period until the combination changes such that a division stripe is unliable to be visually recognized by an observer is important. The larger the number of patterns of the combination of the divided video signals and the buffer circuits is, the more unliable a division stripe is to be visually recognized by an observer, which is preferable. The time period until the combination changes is preferably as short as possible, and is preferably {fraction (1/20)} sec. or shorter.
According to the present invention, when divided driving is performed, a division stripe is unliable to be visually recognized by an observer. Further, since divided driving is performed, images having many tones can be displayed with a high precision and with a high resolution.
The structure of the present invention is as follows.
According to an aspect of the present invention, a semiconductor display device comprising m buffer circuits and a source signal line driving circuit is provided, wherein the m buffer circuits correspond to m divided video signals as parallel data, respectively, the m buffer circuits corresponding to the m divided video signals, respectively, replace one another every time when a predetermined time period elapses, the m divided video signals inputted to the m buffer circuits are outputted from the m buffer circuits to be inputted to the source signal line driving circuit, and the m divided video signals inputted to the source signal line driving circuit are sampled and are inputted to given m source signal lines corresponding to the m divided video signals, respectively.
According to another aspect of the present invention, a semiconductor display device comprising a dividing circuit, a first replacing circuit, a second replacing circuit, m buffer circuits, and a source signal line driving circuit is provided, wherein m divided video signals formed by serial-parallel conversion of a video signal are outputted from the dividing circuit, the m divided video signals outputted from the dividing circuit are inputted to the first replacing circuit, the m divided video signals inputted to the first replacing circuit are inputted to the corresponding m buffer circuits, respectively, the m divided video signals inputted to the m buffer circuits are outputted from the m buffer circuits to be inputted to the second replacing circuit, the m divided video signals inputted to the second replacing circuit are inputted to given m divided video signal lines corresponding to the m divided video signals, respectively, the m divided video signals inputted to the m divided video signal lines are inputted to the source signal line driving circuit, sampled, and inputted to given m source signal lines corresponding to the m divided video signals, respectively, and the m buffer circuits corresponding to the m divided video signals replace one another every time when a predetermined time period elapses.
According to still another aspect of the present invention, a semiconductor display device comprising a dividing circuit, a first replacing circuit, m buffer circuits, and a source signal line driving circuit is provided, wherein the source signal line driving circuit has a second replacing circuit, m divided video signals formed by serial-parallel conversion of a video signal are outputted from the dividing circuit, the m divided video signals outputted from the dividing circuit are inputted to the first replacing circuit, the m divided video signals inputted to the first replacing circuit are inputted to the corresponding m buffer circuits, respectively, the m divided video signals inputted to the m buffer circuits are outputted from the m buffer circuits to be inputted to the second replacing circuit, the m divided video signals inputted to the second replacing circuit are sampled and inputted to given m source signal lines corresponding to the m divided video signals, respectively, and the m buffer circuits corresponding to the m divided video signals replace one another every time when a predetermined time period elapses.
The semiconductor display device may be characterized in that replacement of the m buffer circuits corresponding to the m divided video signals, respectively, is controlled by a replacement data circuit.
The semiconductor display device may be characterized in that how the m buffer circuits corresponding to the m divided video signals, respectively, replace one another is determined by a replacement data circuit.
The semiconductor display device may be characterized in that the replacement data circuit comprises a memory circuit and a counter circuit, and a plurality of replacement data having information with regard to the combination of the m buffer circuits corresponding to the m divided video signals, respectively, are stored in the memory circuit, and one of the replacement data is selected by the counter circuit.
According to another aspect of the present invention, a semiconductor display device comprising a multiplexer circuit, 1 D/A conversion circuit, and 1 dividing circuit is provided, wherein the 1 D/A conversion circuit corresponds to 1 digital distribution signal outputted from the multiplexer circuit, respectively, the 1 D/A conversion circuits corresponding to the 1 digital distribution signals, respectively, replace one another every time when a predetermined time period elapses, and the 1 digital distribution signal inputted to the 1 D/A conversion circuit is converted to 1 analog distribution signal and are inputted to the corresponding given 1 dividing circuit, respectively.
The semiconductor display device may be characterized in that liquid crystal is used.
The semiconductor display device may be characterized in that EL is used.
The present invention may be implemented in a computer using the semiconductor display device.
The present invention may be implemented in a video camera using the semiconductor display device.
The present invention may be implemented in a DVD player using the semiconductor display device.